1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device capable of writing/erasing electrical data and storing information even when a power supply source is turned off.
2. Description of the Background Art
A nonvolatile semiconductor memory device, e.g., a flash memory, has a memory cell array with memory cell transistors having floating gates arranged. The flash memory can electrically write/erase data of the memory cells. Recently, such flash memories are widely used for a data storage application of temporarily storing data in a nonvolatile manner in a system such as a digital still camera, digital audio, and flash card.
In the flash memory, a writing/erasing operation is performed by applying a high voltage to a floating gate which is insulated by an insulation film from a periphery portion in the memory cell transistor to charge or discharge electrons so that the threshold voltage of the memory cell transistor is changed. In the flash memory used for the data storage application, unlike in the conventional application of retaining a program for operating a system, for example, a data unit (the number of memory cells that are collectively processed) not only to be written but also to be erased is desirably small because the writing operation per se must be frequently performed.
FIG. 22 is a schematic block diagram showing an arrangement of a memory cell array of an AND flash memory.
A memory cell MC001 is a floating gate type transistor having a gate, drain and source. Memory cell MC001 has its gate connected to a word line WL(0), its drain connected to a global bit line GBL1 through a sub bit line SBL and a select transistor STR1, and its source connected to a source line SL through a select transistor STR2. 128 memory cells are connected to sub bit line SBL, and 128 word lines form one physical unit. This is referred to as xe2x80x9ca physical block.xe2x80x9d
The writing/erasing operation with respect to the memory cells is usually performed on every word line (hereinafter referred to as xe2x80x9cone sectorxe2x80x9d). The writing operation is performed by applying a positive high voltage (of for example 18 V) to a word line to increase the threshold value of the memory cell.
It is noted that a positive writing preventing voltage (of for example 6 V) is applied to the memory cells to which data is not to be written so as to prevent increase in the threshold value.
The erasing operation is performed by applying a negative high voltage (of for example xe2x88x9217 V) to the word line to decrease the threshold value of the floating gate transistor forming the memory cells.
The writing/erasing operation is automatically performed by a control circuit in the flash memory. In the automatic erasing operation, an operation of determining as to if the memory cell has attained to a threshold value in a desired range (hereinafter referred to as xe2x80x9ca verify operationxe2x80x9d), such as an operation of applying an erasing pulse to a target sector, is repeated. Then, the operation is stopped when the threshold values of all memory cells fall in the desired range, and the completion of the erasing operation is notified to an external system.
When the system requests writing of a data unit greater than one sector, the writing time can be reduced by performing the automatic erasing operation simultaneously on a plurality of sectors. The automatic erasing for every sector is referred to as xe2x80x9csector erasing,xe2x80x9d whereas the automatic erasing performed simultaneously on the plurality of sectors is referred to as xe2x80x9cblock erasing.xe2x80x9d
FIG. 23 is a graph showing a relationship between a threshold value distribution of the memory cell transistors in a block (a plurality of sectors) to be erased and a verify voltage.
FIG. 24 is a flow chart showing an exemplary operation of the block erasing (when one block includes 8 sectors).
Referring to FIGS. 23 and 24, when the block erasing operation is started (a step S1000), a sector address is reset such that AX=0 (a step S1002).
Thereafter, erasing pulses are applied collectively to eight sectors (a step S1004) and, successively, a determination is made as to if the threshold voltages of the memory cells in the first sector have become for example equal to or smaller than 1.6 V (hereinafter indicated as VF1) (this operation is hereinafter referred to as xe2x80x9cerasing verifyxe2x80x9d) (a step S1006).
If it is determined that the threshold voltage has not become equal to or smaller than a potential VF1 as a result of the erasing verify, a process returns to step S1004. Such pulse application and erasing verify are repeated. If it is determined that the threshold voltages of all memory cells in the first sector have become equal to or smaller than potential VF1 (1.6 V) (a step S1006), a determination is made as to if an erasing operation on eight sectors has been completed (a step S1008).
If it is determined that the process on eight sectors has not yet been completed, the sector address is incremented (a step S1010), and step S1006 is performed on the second sector, so that a verify operation is performed as in the case of the first sector.
If it is determined that the erasing verify has been performed on all of the eight sectors in a step S1008, the sector address is reset again (a step S1012).
Thereafter, an operation of checking as to if there is any memory cell of which threshold voltage has become too low (hereinafter referred to as xe2x80x9cover-erasing verifyxe2x80x9d) (a step S1014).
If it is determined that the threshold voltage has become too low as a result of the over-erasing verify operation (step S1014), a writing operation is selectively performed on the memory cell that has failed the over-erasing verify, i.e., the memory cell of which threshold voltage has become equal to or smaller than 0.9 V (hereinafter indicated as VF2) (a step S1012).
A determination is made as to if the threshold voltage has increased at least to potential VF2 by the above mentioned selectively performed writing operation (a step S1022) and, if the threshold value has not increased at least to potential VF2, the selectively performed writing process performed again (step S1020). On the other hand, if it is determined that the threshold voltage has become at least potential VF2 (step S1022), it is again verified as to if there is any cell of which threshold value has become at least 1.9 V (hereinafter indicated as VF3) (this operation is hereinafter referred to as xe2x80x9cover-writing verifyxe2x80x9d) (step S1024).
If it is determined that the threshold value is at least potential VF2 and at most potential VF3 as a result of the over-writing verify, the process proceeds to a step S1016.
Meanwhile, the process also proceeds to step S1016 even if it is determined that the threshold voltage is not at most potential VF2 as a result of the over-erasing verify in step S1014.
A determination is made as to if the over-erasing verify has been performed on eight sectors in step S1016 and, if the process on the eight sectors has not yet been completed, the sector address is incremented (step S1018) and the process returns to the step of the over-erasing verify (step S1014).
If it is determined that the process on the eight sectors has been completed (step S1016), the erasing operation normally ends (a step S1030).
In the step S1024, if the overwriting verify reveals that the threshold value exceeds the potential VF3 as a result of the overwriting caused by the writing verify so performed that the threshold values are rendered above the potential VF2, the erasing operation abnormally ends (step S1026)
In the erasing verify operation, as shown in FIG. 22, the voltage of the selected word line of the sector to be subjected to the erasing verify is set such that VF1=1.6 V, whereas the voltage of the non-selected word lines of other sectors is set such that VF0=xe2x88x922 V.
The global bit line is precharged to about 1 V. When select transistors STR1 and STR2 are turned on, electric charges are discharged from the bit line if the threshold value of the memory cells of the target sector is at most potential VF1.
However, if any memory cell comes to have a threshold voltage of at most potential VF0 other than that in the sector to be verified by simultaneous application of erasing pulses to a plurality of sectors, that cell is always maintained in an on state even if the word line voltage VF0 equals to xe2x88x922 V (the state is hereinafter referred to as xe2x80x9ca deplete statexe2x80x9d). Thus, even if the threshold voltage of the memory cells of the sector to be subjected to the erasing verify is at least VF1, the result of the erasing verify turns out to be xe2x80x9cpassxe2x80x9d because it seems apparently normal.
FIG. 25 is a graph showing a distribution of threshold voltages when an erasing voltage is applied to one sector, where a distribution width is assumed for example 2 V in average.
FIG. 26 is a graph showing a distribution of threshold values for every block after block erasing is performed on a plurality of sectors.
In block erasing, if a variation in erasing characteristics of sectors is large and a distribution of the threshold values is at least 1.6 V as shown in FIG. 26, a memory cell in a deplete state is caused, whereby the erasing verify cannot be normally performed as described above.
FIG. 27 is a diagram shown in conjunction with a path of a current leaking from a global bit line during erasing verify due to the above mentioned memory cell in the deplete state.
Referring to FIG. 27, since a memory cell MC002 is in the deplete state, the potential of word line WL(0) corresponding to a target sector is VF1. Thus, even if the potential of word line WL(1) corresponding to the non-target sector is VFO (xe2x88x922 V), memory cell MC002 is rendered conductive.
Accordingly, even if the threshold level of memory cell MC001 is higher than VF1, electric charges flow from global bit line BL, so that the threshold level of memory cell MC001 is determined, apparently as being lower than VF1.
As described above, although non-selected word line voltage VF0 during erasing verify is for example xe2x88x922 V, if non-selected word line voltage VF is further reduced, a voltage stress (hereinafter referred to as xe2x80x9cdisturbxe2x80x9d) close to the voltage applied to the memory cell during erasing is applied to the non-selected memory cell transistors. Thus, it is desired that a decrease in potential VF0 is minimized.
A possible method may be to decrease voltage VF0 of the non-selected word line only for the sector in the block to be erased of physical blocks. However, the structure and operation of the circuit may disadvantageously become complicated if two potentials VF0 are set within the same physical block.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of normally performing block erasing and minimizing an adverse affect of disturb despite a variation in erasing characteristics of sectors.
In short, the present invention is a nonvolatile semiconductor device including a memory cell array, a plurality of bit lines, a plurality of word lines, a data detection circuit, an internal power supply circuit, a selection circuit, and an internal control circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix. Each memory cell includes a memory cell transistor capable of changing a threshold value in accordance with an applied control potential.
The plurality of bit lines are arranged corresponding to columns of the memory cell array for transmitting data stored in the memory cell transistors. The plurality of word lines are arranged corresponding to rows of the memory cell array for transmitting a control potential and reading potential to the memory cell transistors.
The data detection circuit detects stored data which has been read out through the bit line.
The internal power supply circuit can generate a control potential for an erasing operation on stored data of the memory cell and variably generate a first potential to be applied to selected memory cell and a second potential to be applied to the non-selected memory cell during the reading operation.
The selection circuit selectively supplies the potential generated by the internal power supply circuit to the memory cell.
The internal control circuit can control the operation of the nonvolatile semiconductor memory device and the selection circuit for selectively applying the control potential to the block to be erased. The block to be erased includes a plurality of memory cells connected to a prescribed number of word lines of the plurality of word lines.
The internal control circuit applies the first potential to any one of word lines in the block to be erased and also applies the second potential, which has been updated such that none of a plurality of memory cells belonging at least to the block to be erased is conductive, to the remaining word lines in the block to be erased for verifying erasing based on the detection result of the data detection circuit.
Accordingly, advantage of the present invention is that erasing verify can be normally performed even if there is a depleted cell since a potential of at most a threshold value of the depleted memory cell transistor is applied to the non-selected word line. In addition, since the voltage of the non-selected word line is decreased only when there is a depleted cell, the device is disturbed for a less amount of time than when the non-selected word line is initially set at a low voltage during erasing verify.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.